Category: Past Projects

  • Controlling Uncertainty and Handling Variability in System-Level Dynamic Power Management

    Project Summary: Variability represents diversity or heterogeneity in a well-characterized population. Fundamentally a property of Nature, variability is usually not reducible through further measurement or study. For example, different dies have different leakage power dissipations, no matter how carefully we measure them. Uncertainty represents partial ignorance or lack of perfect information about poorly-characterized phenomena or…

  • Design Methodologies and Techniques for Optimizing Power Consumption and Performance in Pipeline Circuits

    Project Summary: Excessive power dissipation and resulting temperature rise have become one of the key limiting factors to processor performance and a significant component of its cost. In modern microprocessors, expensive packaging and heat removal solutions are required to achieve acceptable substrate and interconnect temperatures. Due to their high utilization, pipeline circuits of a high-performance…

  • Performance and Reliability Analysis and Optimization in Sub-45nm CMOS Circuits

    Project Summary: With the CMOS technology in the nanometer regime, reliability is becoming a major design concern. It seems in future designer will need to make power-performance-reliability tradeoffs at all levels of the VLSI circuit and system design. In this area our current research focuses on building accurate, fast and easy to use fault and…

  • Apollo Testbed

    We research three major areas in low power design of VLSI circuits and systems: software and system level power prediction and optimization, architectural/behavioral power estimation and optimization, and system-level dynamic power management. We investigate the problem of simultaneous scheduling and mapping of the computational and communication processes in a generalized task flow graph to HW/SW…

  • Analysis and Design Techniques for Battery-Powered Digital CMOS Circuits

    In the past, the major concerns of the VLSI designer were area, speed, and cost; power consideration was typically of secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to other design considerations. Several factors have contributed to this trend, including the remarkable success and…

  • Design Methodologies and Techniques for Temperature-dependent Reliability, Performance and Signal Integrity Analysis and Optimization of VLSI Interconnects

    Due to the ever-increasing failure rates in DSM interconnects, interconnect reliability has become a critical design concern in today’s VLSI circuits. However, interconnect reliability and performance (i.e., speed) are tightly coupled and any approach to improve one metric has to consider its effect on the other. Temperature plays a very important role in determining both…

  • Power-Aware Memory Bus Encoding

    This research develops encoding techniques to minimize the switching activity on a time-multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we will…

  • Apollo: Adaptive Power Optimization and Control for the Land Warrior

    Project URL: Apollo Testbed The Apollo project aims at significantly reducing power dissipation of next-generation mobile DoD computing and communication systems by means of operating system-directed power management, power-aware software compilation, and system-level synthesis and optimization of the integrated hardware/software platform subject to performance and quality-of-service constraints. We consider dynamic power management techniques and study the…

  • Low-Power Fanout Optimization

    Low-Power Fanout Optimization Using MTCMOS and Multi-Vt Techniques Although much research has been done to address fanout optimization problem in VLSI circuits, there is little work on low power fanout optimization. More specifically, since both capacitive and leakage power dissipation of a fanout chain are proportional to its area, it has been widely accepted that…