Due to the ever-increasing failure rates in DSM interconnects, interconnect reliability has become a critical design concern in today’s VLSI circuits. However, interconnect reliability and performance (i.e., speed) are tightly coupled and any approach to improve one metric has to consider its effect on the other. Temperature plays a very important role in determining both circuit reliability and performance. The proposed research focuses on detailed yet efficient characterization and quantification of electromigration (EM) and thermomigration (TM) induced failures in VLSI interconnect as well as design automation techniques to combat and control these failures. These techniques will work in a two-dimensional tradeoff space of performance and reliability (PR-space). The proposed research is expected to advance our understanding of EM and especially TM-induced failures in integrated circuits (IC’s) and, at the same time, produce guidelines, algorithms, and tools for achieving a non-dominated operating point in the PR-space.
Our work also focuses on the analysis and modeling of non-uniform chip temperature profile and the study of its effects on different aspects of signal integrity in very high-performance VLSI interconnects. First, we will develop computationally efficient methods to calculate the thermal profile of VLSI interconnect lines. A temperature-dependent distributed RC interconnect delay model will be developed next. The model can be applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact of these thermal non-uniformities on signal integrity issues. Using this model, we will show that global nets (including clock and power/ground distribution networks as well as long busses and set/reset lines) are the nets that are the most vulnerable to the thermal non-uniformities in the substrate. We will therefore develop computer-aided design techniques for constructing a thermally driven zero skew clock routing tree, a power/ground distribution network, optimal buffer insertion in long interconnect lines, and, more generally, chip-level dynamic thermal management policies.