Power-Aware Memory Bus Encoding

This research develops encoding techniques to minimize the switching activity on a time-multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we will develop an optimal encoding, PYRAMID code. Extensions of the basic code address different types of DRAM devices and bus architectures, and explore static vs. dynamic coding schemes. To minimize internal switching activity, we propose scattered paging and redundant coding techniques for both random and sequential access patterns. The proposed codes are expected to reduce power dissipation on the memory bus by a factor of two or more.

We also develop encoding techniques for minimizing the switched capacitance on a non-multiplexed address bus between the processor and static memory. More precisely, we have developed the ALBOZ code, which is constructed based on transition signaling and the limited-weight codes, and with enhancements to make it adaptive and irredundant, results in up to 87% reduction in the bus switching activity at the expense of a small area overhead for realizing the encoder/decoder circuitry. Furthermore, building on T0 and Offset-Xor encoding techniques, we have developed three irredundant bus-encoding techniques that decrease switching activity on the memory address bus by up to 83% without the need for redundant bus lines. The power dissipation of encoder and decoder circuitry has also been calculated and shown to be small in comparison with the power savings on the memory address bus itself.