Analysis and Design Techniques for Battery-Powered Digital CMOS Circuits

In the past, the major concerns of the VLSI designer were area, speed, and cost; power consideration was typically of secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to other design considerations. Several factors have contributed to this trend, including the remarkable success and growth of the class of battery-powered, personal computing devices and wireless communications systems that demand high-speed computation and complex functionality with low power consumption. In these applications, extending the battery service life is a critical design concern. There also exists a significant pressure for producers of high-end products to reduce their power consumption. The main driving factors for lower power dissipation in these products are the cost associated with packaging and cooling as well as the circuit reliability.

Our research focuses on the problem of maximizing the battery service life in battery-powered CMOS circuits. In particular, we recently proposed an integrated model of the VLSI hardware and the battery sub-system that powers it. We showed that, under this model and for a fixed operating voltage, the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a super-linear function of the average discharge current. Furthermore, even if the average discharge current remains the same, different discharge current profiles (distributions) may result in very different battery lifetimes. The maximum battery life is achieved when the variance of the discharge current distribution is minimized. Finally, we demonstrated that accounting for the dependence of battery capacity on the average discharge current changes the shape of the energy-delay trade-off curve and hence the value of the operating voltage that results in the optimum energy-delay product for the target circuit. Consequently, we proposed a more accurate metric (i.e., the battery discharge rate times delay product as opposed to the energy-delay product) for comparing various low power optimization methodologies and techniques targeted toward battery-powered electronics. Analytical derivations as well as simulation results demonstrate the importance of correct modeling of the battery-hardware system as a whole.

Our research has far-reaching implications for the design of battery-powered electronics by shifting the focus from power and energy minimization to battery service life maximization. It also brings up a number of new and exciting research problems, including, but not limited to, static and dynamic voltage scaling rules to maximize the battery service life subject to performance constraints, optimal choice of battery cells for a given VLSI circuit, circuit and architectural design of the VLSI system hardware to match the output characteristics of the battery cells that power it, use of multiple battery cells and dynamic power management schemes to maximize the service life of the battery subsystem, and even integrated on-chip battery-hardware design (micro-batteries for micro-electronics).

Portable electronic devices tend to be much more complex than a single VLSI chip; They contain many components, ranging from digital and analog to electro-mechanical and electro-chemical. Hence reducing power consumption only in the digital VLSI circuits is insufficient. System designers have started to respond to the requirement of power-constrained system designs by a combination of technological advances and architectural improvements. Dynamic power management which refers to selective shut-off or slow-down of system components that are idle or underutilized has proven to be a particularly effective technique. Incorporating an effectual dynamic power management scheme in the design of an already-complex system is a difficult process that may require many design iterations and careful debugging and validation. The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing certain performance and power consumption level. The policy determines the type and timing of theses transitions based on the system history, workload and performance constraints.

Our research focuses on the development of an abstract stochastic model of a power-managed electronic system and formulating the problem of system-level power management as a stochastic optimization problem based on the theories of continuous-time Markov decision processes and stochastic networks. This problem will be solved exactly and efficiently using a “policy iteration” approach. Extensions to more complex systems, non-stationary system behavior and non-Markovian decision making will be considered.