Category: Coldflux: Tools For SFQ Logic Design

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) In this project new algorithms for placement and clock network synthesis for large scale SFQ circuits a re developed and implemented. The goal is to maximize the circuit performance in terms of maximum clock frequency, considering special characteristics of SFQ technology.

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Development of a routing tools for single flux quantum (SFQ) circuits. The routing tools aims at finding connection wire paths of all nets of a SFQ circuit while satisfying design rule check. The following is for elaboration: The routing tools are further optimized to identify critical nets with…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) This project is about designing suitable computer aided-design (CAD) software tools to support design automation of superconducting single flux quantum circuits. The main focus is on logic and behavioral level synthesis. This includes designing algorithms and implementing them using C/C++ and Python programming languages, and it involves verification…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Due to fabrication uncertainties, it is important to have cells that can tolerate variations. For this project, we introduce a hybrid optimization algorithm for improving critical parameter margins of the cells. With Monte Carlo simulations, we show that increased critical margins improve the parametric yield. Related work:

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Due to the lack of three-terminal device like MOSFET in CMOS circuits in superconducting electronics, it is difficult to conceive a superconducting FPGA which provides significantly cheaper solutions for various applications. Our work is focused on proposing designing FPGA for superconducting circuits using magnetic Josephson junctions and energy-efficient…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) we address the problem of deriving a functional description of a circuit from an unstructured netlist by leveraging deep learning and circuit representations based on convolutional neural networks (CNNs). In doing so, we are motivated by the state-of-the-art performance of machine learning (ML) techniques, based on both convolutional…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Objective of this project is to develop the post-synthesis verification techniques for SFQ circuits. As part of this work, we developed a logical equivalence checking (LEC) approach that would check the equivalence of a post-synthesis gate level netlist of a target SFQ circuit against an initial Boolean network…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Description: As Moore’s law dying for CMOS, novel technology with higher operation rate, better power efficiency and scale-ability is badly demanded for future chips. SFQ is one of the most promising saplings using single quantum flux as the compute unit, holding an advantage of fast speed and low…

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Development of timing analysis tool to provide timing information for a given post-synthesis/placement/routing circuits. It implements static timing analysis and statistical static timing analysis, prunes unimportant paths, reports setup/hold time violations, provides timing information to ensure timing closure of placement/routing. Related work: 

Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Description: We plan to exploit the nature of each gate being clocked in SFQ circuits and use this gate level pipelined nature of SFQ logic cells to design a ALU to have better throughput (qBSA). We also, plan to carry forward this research to evaluate the performance of…