Sponsor: Intelligence Advanced Research Projects Activity (IARPA)
Description: We plan to exploit the nature of each gate being clocked in SFQ circuits and use this gate level pipelined nature of SFQ logic cells to design a ALU to have better throughput (qBSA). We also, plan to carry forward this research to evaluate the performance of the ALU for Data dependent operations.
Related work:
- Souvik Kundu, Gourav Datta, Peter A. Beerel, Massoud Pedram, “qBSA: Logic design of a 32-bit block-skewed RSFQ arithmetic logic unit”, in IEEE ISEC 2019.