Biographical Sketch

I was born in Ahwaz. I received the B.Sc. and M.Sc. degrees in Electrical Engineering–Electronics from Ferdowsi University of Mashhad and University of Tehran, Iran in 2014 and 2017, respectively. I am currently a Ph.D. student in Electrical Engineering under supervision of Prof. Massoud Pedram at University of Southern California where I work as a work assistant with the SPORT lab since 2017. The primary objective of my research is to develop techniques and algorithms (finally become available as computer-aided design, CAD, tools) useful for low power and high performance advanced device, circuits, architecture and system


University of Southern California

Doctor of Philosophy in Electrical Engineering current

University of Southern California

Master of Science in Computer Science current

University of Southern California

Master of Science in Electrical Engineering 2020

University of Tehran

Master of Science in Electrical Engineering 2017


For complete list of my publication, you can visit my google scholar page.

Book Chapter

Inverter-based Memristive Neuromorphic Circuit for Ultra-low-power IoT Smart Applications Arash Fayyazi, Mohammad Ansari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. IET Book on Hardware Architectures for Deep Learning. [link]

Peer-Reviewed Journals

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits Mohammad Ansari, Arash Fayyazi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS I), 2019. [link]

SystemVerilog modeling of SFQ and AQFP circuits Ramy N Tadros, Arash Fayyazi, Massoud Pedram, Peter A Beerel. IEEE Transactions on Applied Superconductivity, 2019. [link] [Code]

An Ultra-Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors Arash Fayyazi, Mohammad Ansari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. IEEE internet of things journal, 2018. [PDF]

PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits Mohammad Ansari, Arash Fayyazi, Ali Banagozar, Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. [PDF] [Code]

Refereed Full-Length Conference Proceedings

SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning Mahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, and Massoud Pedram. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020. [PDF]

HIPE-MAGIC: A Technology-Aware Synthesis and Mapping Flow for Highly Parallel Execution of Memristor-Aided LoGIC Arash Fayyazi, Amirhossein Esmaili Dastjerdi, Massoud Pedram. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2020. [PDF]

qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework Shahin Nazarian, Arash Fayyazi, Massoud Pedram. IEEE 37th International Conference on Computer Design (ICCD), 2019. [link]

qEC: A Logical Equivalence Checking Framework Targeting SFQ Superconducting Circuits Arash Fayyazi, Shahin Nazarian, Massoud Pedram. IEEE International Superconductive Electronics Conference (ISEC), 2019. [link]

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity Arash Fayyazi, Souvik Kundu, Shahin Nazarian, Peter A Beerel, Massoud Pedram. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. [PDF]

A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning Karunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram, Shahin Nazarian. ACM Great Lakes Symposium on VLSI (GLSVLSI), 2019. [link]

Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations Arash Fayyazi, Soheil Shababi, Pierluigi Nuzzo, Shahin Nazarian, Massoud Pedram. IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019. [link] [Code] [DAC'20 Young Fellow Poster] [DAC'20 Young Fellow Video]

VeriSFQ: A semi-formal verification framework and benchmark for single flux quantum technology Alvin D Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian. IEEE 20th International Symposium on Quality Electronic Design (ISQED), 2019. [PDF]

SEERAD: A high speed yet energy-efficient rounding-based approximate divider Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016. [PDF]


Low-power and Area-efficient Neuromorphic Systems for Edge Computing

Nowadays, the analysis of massive amounts of data is generally performed by remotely accessing large cloud computing resources. The cloud computing is however hindered by the security limitation, bandwidth bottleneck, and high cost. In addition, while unstructured a multimedia data (video, audio, etc.) are straightforwardly recognized and processed by the human brain, conventional digital computing architecture has major difficulties in processing this type of data, especially in real time. Another major concern for data processing, especially in the case of Internet of Things (IoT) devices which do distributed sensing and typically rely on energy scavenging, is power consumption. One of the ways to deal with the cloud computing bottlenecks is to use low-power neuromorphic circuits, which are a type of embedded intelligent circuits aimed at real-time screening and preprocessing of data before submitting the data to the cloud for further processing. We developed an ultra-low-power analog neuromorphic circuits for processing sensor data in the IoT devices where low-power, yet area-efficient computations are required. To reduce power consumption without losing performance, we resort to a memristive neuromorphic circuit that employs inverters instead of power-hungry op-amps. We also presented ultra-low-power mixed-signal analog-to-digital converters (ADC) and digital-to-analog converters (DAC) to make the analog neuromorphic circuit connectable to other digital components such as an embedded processor.

Deep Learning-Based Digital Circuit Design and Verification Flow

as CAD/VLSI engineers, we are fortunate to make advances to the application of existing ML for CAD algorithm (e.g., functional verification and circuit recognition) as well as use these advances to build new hardware that will further accelerate the application of ML. This yields a spiral of development that will hopefully provide insight into both problems and improve the optimal point of convergence for a wide variety of fields. So far, I implement a deep learning framework that relies on data structure, termed level-dependent decaying sum (LDDS) existence vector, and novel sparse mapping algorithm, which allows to only encode information about the logic cell functionality, to recognize the functionality of digital datapath circuits. We also propose a novel learning-based framework in which we incorporate RL and DNNs for accelerating the verification process of complex sequential designs.

A Superconducting Circuit Design and Verification Flow

The overarching goal of this project that is named as “SuperTools program” by IARPA is the creation of a full suite of design tools that will facilitate the design of an SCE central processing unit (CPU) as well as other complex SCE circuits. The art of digital design for SCE has seen very simple handcrafted circuits run with clock speeds in excess of 500 GHz. However, even modestly sized handcrafted circuits sometimes fail to work at all. Whether very fast and low power complex SCE circuits can be designed with suitable modified Computer Aided Design (CAD) tools is the challenge that the SuperTools program must address. My responsibilities in project is two folds, 1) Hardware description language (HDL) modeling of gates for behavioral and functional simulation and verification of large netlists, 2) Verifying the correct functionality of the designed circuits.

Syhnthesis and Mapping Framework for Processing-in-Memory

Recent efforts for finding novel computing paradigms that meet today’s design requirements have given rise to a new trend of processing-in-memory relying on non-volatile memories. In this work, we present HIPE-MAGIC, a technology-aware synthesis and mapping flow for highly parallel execution of the memristor-basedlogic. Our framework is built upon two fundamental contributions: balancing techniques during the logic synthesis, mainly targetingvbenefits of the parallelism offered by memristive crossbar arrays(MCAs), and an efficient technology mapping framework to maximize the performance and area-efficiency of the memristor-based logic.