Tag: Featured
-
USC SPORT: System Power Optimization and Regulation Technologies
—
Project URL: SPORT Lab We investigate power estimation and low power design of CMOS VLSI circuits and systems all different abstraction levels. Our emphasis is on developing mathematically rigorous analysis and optimization algorithms and power-aware design methodologies for solving various problems of practical interest and import. Our most recent work has focused on energy-efficient enterprise computing,…
-
Accurate gate modeling under variation with neural networks
—
Deeply scaled FinFET devices are the optimal choice for low power applications based on their specific characteristics over conventional MOSFET devices. However, these devices are very sensitive to process variation and exhibit non-linear timing and power behavior. Due impact of several number of variation parameters, it is not-practical for the conventional industrial characterization process (e.g.…
-
Energy-aware Task Scheduling in Real-Time Systems with Hard Deadline Constraints
—
Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the…
-
Design of Modular Multiplication
Development of efficient Montgomery/Barrett modular multiplication to reduce computation latency or save hardware area. It includes a new algorithm to parallelize the computation of quotient and intermediate result, speed up the expression (A+B)*C, etc. Related work:
-
Algorithm-Architecture Co-Design for Energy-Efficient and Reliable Machine Learning Models
Sponsor: National Science Foundation (NSF) The broader scope of this research includes: a) Energy-efficient architecture and algorithm co-design for DNN training to yield compressed models, b) Efficient model compression to retain its robustness, c) Model compression of brain-inspired deep SNNs.Related work:
-
Energy-Efficient, Low-Latency Realization of Neural Networks Through Boolean Logic Minimization
Sponsor: TBD To cope with computational and storage complexity of deep neural networks, this project focuses on a training method that enables a radically different approach for realization of deep neural networks through Boolean logic minimization. The aforementioned realization completely removes the energy-hungry step of accessing memory for obtaining model parameters, consumes about two orders…
-
Best Paper Award at the IEEE Computer Society Annual Symposium on VLSI
—
in NewsMembers of the SPORT team: A. Shafaei, Y. Wang, and X. Lin received the Best Paper Award at the IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida, USA, July 9-11, 2014.
-
Prof. Pedram concluded his term as the Editor-in-Chief of the ACM Trans. on Design Automation of Electronic Systems
—
in NewsProf. Pedram concluded his term as the Editor-in-Chief of the ACM Trans. on Design Automation of Electronic Systems, in May 2014. He had served in that position from Jun. 2008.
-
Prof. Pedram concludes his term as the Inaugural Editor-in-Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems
—
in NewsProf. Pedram concluded his term as the Inaugural Editor-in-Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems in Dec. 2013. He had served in that position from Jan. 2010.