Sponsor: Seminconductor Research Corp.
Project Summary The down scaling of layout geometries to 45nm and below has resulted in a significant increase in the packing density and the operational frequency of VLSI circuits. The conventional static timing analysis (STA) techniques model signal transitions as saturated ramps with known arrival and transition times and propagate these timing parameters from the circuit primary inputs to the primary outputs. However the different waveforms with identical arrival time and slew (transition) time applied to the input of a logic cell or an interconnect line can result in very different propagation delays through the component depending on the exact form of the applied signal waveform. In addition, as we move towards the 45nm and lower minimum feature sizes for the devices, process variations are becoming an ever increasing concern for the design of high performance integrated circuits. The process variations can cause excessive uncertainty in timing calculation, which in turn calls for sophisticated analysis techniques to reduce the uncertainty.
Recent Results of the Current Source Model-Based Approach for Timing Analysis — Our work focuses on the development of an accurate current source model of a CMOS logic cell with extensions to handle multiple input switching and statistical parameter variability. The work also includes development of efficient methods to generate the CSMs of logic cells, which are typically present in a standard cell library. The work addresses integration of CSMs of logic cells with a waveform propagation engine in order to produce a highly efficient and robust CSM-based static timing analyzer.