Performance and Power Efficiencies of Network On-Chip

—

in

Sponsors: National Science Foundation (the Software and Hardware Foundations).

Improving the Quality of Service in Application Mapping on NoC-Based Multi-Core Platforms

With tens to possibly hundreds of cores integrated in current and future multiprocessor systems-on-chips (MPSoCs) and chip-multiprocessors (CMPs), multiple applications usually run concurrently on the system. However, existing mapping methods for reducing overall packet latency cannot meet the requirement of balanced on-chip latency when multiple applications are present. We address the looming issue of balancing minimized on-chip packet latency with performance-awareness in the multi-application mapping of CMPs.

The approach of adding express channels to the tile-based NoCs has gained increasing attention. However, this approach also greatly changes the packet delay estimation and traffic behaviors of the network, both of which have not yet been exploited in existing mapping algorithms. Therefore, we explore the opportunities in optimizing application mapping for express channel-based on-chip networks.Related work:

  • D. Zhu, L. Chen, S. Yue, and M. Pedram. “Application mapping for express channel-based networks-on-chip,” Proc. of Design Automation and Test in Europe, Mar. 2014.
  • D. Zhu, S. Yue, L. Chen, T. Pinkston, and M. Pedram. “Balancing On-Chip Network Latency in Multi-Application Mapping for Chip-Multiprocessors,” Proc. of Int’l Parallel and Distributed Processing Symposium, May 2014.
  • D. Zhu, L. Chen, T. Pinkston, and M. Pedram. “Temperature-aware application mapping for NoC-based many-core processors,” To appear in Proc. of Design Automation and Test in Europe, Mar. 2015.

Improving the Power Efficiencies of On-Chip Networks

Compared with traditional bus structures, the relatively complex NoCs with routers and links can draw a substantial percentage of chip power. An effective approach to reduce NoC power consumption is to apply power gating techniques. We explore different power gating schemes of on-chip networks to achieve low energy consumption as well as small latency penalties.Related work:

  • L. Chen, D. Zhu, M. Pedram, and T. M. Pinkston. “Power punch: towards non-blocking power-gating of NoC routers,” To appear in Proc. of IEEE International Symposium On High Performance Computer Architecture, Feb. 2015.
  • S. Yue, L. Chen, D. Zhu, T. M. Pinkston, and M. Pedram. “Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness,” Proc. of the Int’l Symposium on Low Power Electronics and Design, Aug. 2014.