Alireza Shafaei

An Integrated Row-based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

Soheil Nazar Shahsavani, Ting-Ru Lin, Alireza Shafaei, Coenrad Fourie, and Massoud Pedram

IEEE Transactions on Applied Superconductivity, 27(4):1-8, June 2017

A Thermally-Aware Energy Minimization Methodology for Global Interconnects

Soheil Nazar Shahsavani, Alireza Shafaei, Shahin Nazarian, and Massoud Pedram

Design Automation and Test in Europe (DATE), March 2017

Pilot Register File: Energy Efficient Register File for GPUs

Mohammad Abdel-Majeed, Hyeran Jeon, Alireza Shafaei, Murali Annavaram, and Massoud Pedram

23rd IEEE Symposium on High Performance Computer Architecture (HPCA), February 2017

Design of Multiple Fanout Clock Distribution Network for Rapid Single Flux Quantum Technology

Naveen Katam, Alireza Shafaei, and Massoud Pedram

22nd Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017

Minimizing the Energy-Delay Product of SRAM Arrays using a Device-Circuit-Architecture Co-Optimization Framework

Alireza Shafaei, Hassan Afzali-Kusha, and Massoud Pedram

53rd Design Automation Conference (DAC), June 2016

Energy-Efficient Cache Memories using a Dual-Vt 4T SRAM Cell with Read-Assist Techniques

Alireza Shafaei and Massoud Pedram

Design Automation and Test in Europe (DATE), March 2016

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations

Alireza Shafaei, Shuang Chen, Yanzhi Wang, and Massoud Pedram

20th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2015

Low Write-Energy STT-MRAMs using FinFET-based Access Transistors

Alireza Shafaei, Yanzhi Wang, and Massoud Pedram

32nd IEEE International Conference on Computer Design (ICCD), October 2014

Best Paper Award

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-scaled FinFET Devices

Alireza Shafaei, Yanzhi Wang, Xue Lin, and Massoud Pedram

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014

Layout Optimization for Quantum Circuits with Linear Nearest Neighbor Architectures

Massoud Pedram and Alireza Shafaei

IEEE Circuits and Systems Magazine, 16(2):62-74, May 2016.

Squash 2: A Hierarchical Scalable Quantum Mapper Considering Ancilla Sharing

Mohammad Javad Dousti, Alireza Shafaei, and Massoud Pedram

Quantum Information & Computation (QIC), 16(3&4): 332-356, March 2016

Computer-Aided Design for Next-Generation Quantum Computing Systems

Alireza Shafaei, Mohammad Javad Dousti, and Massoud Pedram

New Developments in Quantum Optics Research, Nova Science Publishers, 2015

Cofactor Sharing for Reversible Logic Synthesis

Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram

ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reversible Computation, 11(2): 14:1-14:21, November 2014

Squash: A Scalable Quantum Mapper Considering Ancilla Sharing

Mohammad Javad Dousti, Alireza Shafaei, and Massoud Pedram

24th Great Lakes Symposium on VLSI (GLSVLSI), May 2014

Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits

Hadi Goudarzi, Mohammad Javad Dousti, Alireza Shafaei, and Massoud Pedram

Quantum Information Processing, 13(5): 1267-1299, May 2014

Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram

19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014

Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures

Mehdi Saeedi, Alireza Shafaei, and Massoud Pedram

5th Conference on Reversible Computation (RC), July 2014

Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures

Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram

50th Design Automation Conference (DAC), June 2013

Reversible Logic Synthesis of k-Input, m-Output Lookup Tables

Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram

Design Automation and Test in Europe (DATE), March 2013

Alireza Shafaei

Selected Publications

An Integrated Row-based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

A Thermally-Aware Energy Minimization Methodology for Global Interconnects

Pilot Register File: Energy Efficient Register File for GPUs

Design of Multiple Fanout Clock Distribution Network for Rapid Single Flux Quantum Technology

Minimizing the Energy-Delay Product of SRAM Arrays using a Device-Circuit-Architecture Co-Optimization Framework

Energy-Efficient Cache Memories using a Dual-Vt 4T SRAM Cell with Read-Assist Techniques

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations

Low Write-Energy STT-MRAMs using FinFET-based Access Transistors

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-scaled FinFET Devices

Layout Optimization for Quantum Circuits with Linear Nearest Neighbor Architectures

Squash 2: A Hierarchical Scalable Quantum Mapper Considering Ancilla Sharing

Computer-Aided Design for Next-Generation Quantum Computing Systems

Cofactor Sharing for Reversible Logic Synthesis

Squash: A Scalable Quantum Mapper Considering Ancilla Sharing

Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits

Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures

Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures

Reversible Logic Synthesis of k-Input, m-Output Lookup Tables

Contact Information

Address

Email

Office