The ISCAS format, with the `.isc` file extension, is associated with the ISCAS benchmark circuits, primarily introduced at the International Symposium of Circuits and Systems. These benchmarks, including ISCAS'85 and ISCAS'89, are widely used in the field of electronic design automation (EDA) for testing and evaluating digital circuits and algorithms.
.isc
The ISCAS format typically describes digital circuits in a concise and structured manner, focusing on the gate-level representation of the circuit. Details about the specific syntax and structure used in the ISCAS format can be found in the benchmark documentation and related academic papers.
ISCAS benchmarks are predominantly used for testing digital circuits and algorithms in various areas such as fault simulation, logic synthesis, and optimization. These benchmarks provide a standard set of circuits that help in evaluating and comparing different EDA tools and techniques.
Examples of circuits in the ISCAS format can be found in the documentation of the ISCAS benchmark suites. Researchers and practitioners are encouraged to refer to these examples for a better understanding of the format.
* c17 in ISCAS Format * --------------------------------------------------- * * * total number of lines in the netlist .............. 17 * simplistically reduced equivalent fault set size = 22 * lines from primary input gates ....... 5 * lines from primary output gates ....... 2 * lines from interior gate outputs ...... 4 * lines from ** 3 ** fanout stems ... 6 * * avg_fanin = 2.00, max_fanin = 2 * avg_fanout = 2.00, max_fanout = 2 * * * * * 1 1gat inpt 1 0 >sa1 2 2gat inpt 1 0 >sa1 3 3gat inpt 2 0 >sa0 >sa1 8 8fan from 3gat >sa1 9 9fan from 3gat >sa1 6 6gat inpt 1 0 >sa1 7 7gat inpt 1 0 >sa1 10 10gat nand 1 2 >sa1 1 8 11 11gat nand 2 2 >sa0 >sa1 9 6 14 14fan from 11gat >sa1 15 15fan from 11gat >sa1 16 16gat nand 2 2 >sa0 >sa1 2 14 20 20fan from 16gat >sa1 21 21fan from 16gat >sa1 19 19gat nand 1 2 >sa1 15 7 22 22gat nand 0 2 >sa0 >sa1 10 20 23 23gat nand 0 2 >sa0 >sa1 21 19