BLIF Format Manual

Introduction:

The Berkeley Logic Interchange Format (BLIF) is a file format used for representing digital logic circuits. It is a versatile format that supports a wide range of logic synthesis and simulation applications. BLIF was developed at the University of California, Berkeley, and it has become a standard in the field of electronic design automation (EDA) for representing designs in a tool-independent manner.

File Extension:

.blif

Syntax:

1. Model Declaration:
   • Starts with .model followed by the model name.
   • Example: .model my_circuit
2. Inputs and Outputs:
   • Declared with .inputs and .outputs.
   • Example: .inputs a b c and .outputs z
3. Logic Gates:
   • Described using the .gate keyword or truth tables.
   • Example: .gate AND a=b c
4. Latches:
   • Specified using the .latch keyword.
   • Example: .latch input_gate output_gate type
5. End Model:
   • End of the model is marked by .end.
   • Example: .end

Do's and Don'ts:

• Do:
  • Clearly specify all inputs and outputs.
  • Use .gate for standard gates or truth tables for custom logic.
  • Include .latch for sequential elements.
  • End each model with .end.
• Don't:
  • Avoid ambiguous naming for inputs, outputs, and internal nodes.
  • Don't omit the model declaration at the beginning.
  • Don't leave the model open; always use .end to signify the end.

Example:

# Full-Adder in BLIF format 

.model full_adder
.inputs A B Cin
.outputs Sum Cout
.names A B X1
01 1
10 1
.names A B A1
11 1
.names X1 Cin Sum
01 1
10 1
.names X1 Cin A2
11 1
.names A1 A2 Cout
1- 1
-1 1
.end

# c17 in BLIF Format 

.model c17
.inputs 1GAT(0) 2GAT(1) 3GAT(2) 6GAT(3) 7GAT(4)
.outputs 22GAT(10) 23GAT(9)
.names 3GAT(2) 6GAT(3) 11GAT(5)
11 0
.names 1GAT(0) 3GAT(2) 10GAT(6)
11 0
.names 11GAT(5) 7GAT(4) 19GAT(7)
11 0
.names 2GAT(1) 11GAT(5) 16GAT(8)
11 0
.names 16GAT(8) 19GAT(7) 23GAT(9)
11 0
.names 10GAT(6) 16GAT(8) 22GAT(10)
11 0
.end