Abstract: The success of CMOS has overshadowed nearly all other solid-state device innovations over recent decades. With fundamental CMOS scaling limits close in sight, the time is now ripe to explore disruptive computing technologies. As a viable post-CMOS computing technology, superconductor electronics can deliver ultra-high performance and energy efficiency at scale, thereby paving the way for seminal innovations in integrated electronics, sustainable exascale computing, and acceleration of machine learning. This half-day workshop will cover the challenges and opportunities associated with the first-time design of a superconductive system of cryogenic computing cores (SuperSoCC), which is the focus of a recently awarded NSF Expeditions in Computing award. To demonstrate SuperSoCC, a slew of challenges related to physical scaling, chip-level integration, compact modeling and design tool support, on-chip memory design, architecture design, and full-system design and integration including interfacing to room temperature electronics must be addressed. These issues will be addressed through a series of talks given by experts in the field.
Note: For those registered for virtual attendance, here is theZoom Link