Journal Publications

  1. M. Triki, Y. Wang, A.C. Ammari, and M. Pedram “Hierarchical Power Management of a System with Autonomously Power-Managed Components Using Reinforcement Learning,” To appear in Elsevier Integration, the VLSI Journal, 2014.
  2. A. Shafaei, M. Saeedi, and M. Pedram, “Cofactor Sharing for Reversible Logic Synthesis,” To appear in ACM JETC Special Issue on Reversible Computation, 2014.
  3. Y. Wang, X. Lin, Y. Kim, Q. Xie, M. Pedram, and N. Chang. “Single-source, single-destination charge migration in hybrid electrical energy storage systems,” To appear in IEEE Trans. on VLSI Systems, 2014.
  4. Q. Xie, Y. Kim, Y. Wang, J. Kim, N. Chang, and M. Pedram. “Principles and Efficient Implementation of Charge Replacement in Hybrid Electrical Energy Storage Systems,” To appear in IEEE Trans. on Power Electronics, 2014.
  5. Q. Xie, Y. Wang, M. Pedram. “Designing Soft-Edge Flip-Flop-Based Linear Pipelines Operating in Multiple Supply Voltage Regimes,” To appear in Integration, the VLSI Journal, Elsevier, 2014.
  6. X. Lin, Y. Wang, M. Pedram. J. Kim, and N. Chang. “Designing Fault-Tolerant Photovoltaic Systems,” IEEE Design and Test Magazine, IEEE Design and Test Magazine, Vol. 31, No. 3, Jun. 2014, pp. 1–9.
  7. Y. Wang, X. Lin, Y. Kim, N. Chang, and M. Pedram. “Architecture and control algorithms for combatting partial shading in PV systems,” IEEE Trans. on Computer Aided Design, Vo. 33, No. 6, Jun. 2014, pp. 917–930.
  8. Y. Kim, J. Koh, Q. Xie, Y. Wang, N. Chang, and M. Pedram. “A scalable and flexible hybrid energy storage system design and implementation,” Journal of Power Sources, Vol. 255, No. 1 Jun. 2014, pp. 410-422.
  9. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram. “Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors,” ACM Journal on Emerging Technologies in Computing Systems, Vol. 10, Issue 3, Apr. 2014, Article No. 19.
  10. S. Hatami, M. Helaoui, F. M. Ghannouchi, and M. Pedram. “Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters” IEEE Transactions on VLSI Systems, Vol. 22, No. 4, Apr. 2014, pp. 922-931.
  11. Y. Wang, X. Lin, and M. Pedram. “Adaptive control for energy storage systems in households with photovoltaic modules,” IEEE Trans. on Smart Grid, Vol. 5, No. 2, Mar. 2014, pp. 992-1001.
  12. H. Goudarzi, M. J. Dousti, A. Shafaei Bejestan, and M. Pedram. “Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits,” Springer Journal of Quantum Information Processing, Vol. 13, Jan. 2014, pp. 1267-1299.
  13. W. Lee, Y. Wang, D. Shin, N. Chang, and M. Pedram. “Optimizing the Power Delivery Network in a Smartphone Platform,” IEEE Trans. on Computer Aided Design, Vol. 33, No. 1, Jan. 2014, pp. 36-49.
  14. Y. Kim, Y. Wang, M. Pedram, and N. Chang, “Computer-Aided Design and Optimization of Hybrid Energy Storage Systems,” Now’s Foundations and Trends in Electronic Design Automation, Vol. 7, No. 4, 2013, pp. 247-338.
  15. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram. “Considering the effect of process variations during the ISA extension design flow,” Elsevier Microprocessors and Microsystems,Vol. 37, No. 6-7, Aug.-Oct. 2013, pp. 713-724.
  16. K. Patel, M. Annavaram, and M. Pedram. “NFRA: Generalized Network Flow Based Resource Allocation for Hosting Centers,” IEEE Trans. on Computers, Vol. 62, No. 9, Sep. 2013, pp. 1772-1785.
  17. M. Kamal, A. Yazdanbakhsh, H. Noori, A. Afzali-Kusha, and M. Pedram. “A new merit function for custom instruction selection under an area budget constraint,”Springer Design Automation for Embedded Systems, Sep. 2013.
  18. D. Shin, Y. Kim, N. Chang, and M. Pedram. “Dynamic Driver Supply Voltage Scaling for Organic Light Emitting Diode Displays,” IEEE Trans. on Computer Aided Design, Vol. 32, No. 7, Jul. 2013, pp. 1017-1030.
  19. Q. Xie, Y. Wang, Y. Kim, N. Chang, and M. Pedram. “Charge allocation for hybrid electrical energy storage systems,” IEEE Trans. on Computer Aided Design, Vol. 32, No. 7, Jul. 2013, pp. 1003-1016.
  20. M. Saeedi and M. Pedram. “Linear-Depth Quantum Circuits for n-qubit Toffoli gates with no Ancilla,” Physical Review A, Vol. 87, No. 6, 2013 (arXiv:1303.3557).
  21. A. Abdollahi, M. Saeedi, and M. Pedram. “Reversible Logic Synthesis by Quantum Rotation Gates,” Quantum Information and Computation Journal, Rinton Press, Vol. 13, No. 9-10, pp. 0771-0792, 2013 (arXiv:1302.5382).
  22. H. Abrishami, S. Hatami, and M. Pedram. “Design and Multi-Corner Optimization of the Energy-Delay Product of CMOS Flip-Flops under the NBTI Effect,” IEEE Trans. on Computer Aided Design, Vol. 32, No. 6, Jun. 2013, pp. 869-881.
  23. S. Park, J. Park, D. Shin, Y. Wang, Q. Xie, N. Chang, and M. Pedram “Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors,” IEEE Trans. on Computer Aided Design, Vol. 32, No. 5, May 2013, pp. 695-708.
  24. B. Ghavami, M. Raji, H. Pedram, and M. Pedram. “Statistical functional yield estimation and enhancement of CNFET-based VLSI circuits,” IEEE Trans. on VLSI Systems, > Vol. 21, No. 5, May 2013, pp. 887-900.
  25. Y. Kim, W. Lee, M. Pedram, and N. Chang. “Dual-mode power regulator for photovoltaic module emulation,” Elsevier Applied Energy, Vol. 101, Jan. 2013, pp. 730-739.
  26. B. Afzal, A. Afzali-Kusha, and M. Pedram. “Analytical Modeling of Read Margin Probability Distribution Function of SRAM Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect,” Japanese Journal of Applied Physics, Vol. 51, No. 11, Nov. 2012.
  27. H. Aghababa, B. Ebrahimi, A. Afzali-Kusha, and M. Pedram. “Probability calculation of read failures in nano-scaled SRAM cells under process variations.” Microelectronics Reliability, Vol. 52, No. 11, Nov. 2012, pp. 2805-2811.
  28. M. Pedram. “Energy-Efficient Datacenters,” IEEE Trans. on Computer Aided Design, Vol. 31, No. 10, Oct. 2012, pp. 1465-1484.
  29. H. Aghababa, A. Khosropour, A. Afzali-Kusha, B. Forouzandeh, and M. Pedram. “Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalized extreme value distribution,” IET Computers & Digital Techniques, Vol. 6, No. 5, Sep. 2012, p. 271-373.
  30. D. Shin, Y. Kim, Y. Wang, N. Chang, and M. Pedram. “Constant-Current Regulator-Based Battery-Supercapacitor Hybrid Architecture for High-Rate Pulsed Load Applications,” Elsevier Journal of Power Sources, Vol. 205, May 2012, pp. 516-524.
  31. E. Pakbaznia and M. Pedram. “Design of a tri-modal multi-threshold CMOS Switch with application to data retentive power gating,” IEEE Trans. on VLSI Systems, Vol. 20, No. 2, Feb. 2012, pp. 380-385.
  32. B. Afzal, B. Ebrahimi, A. Afzali-Kusha, and M. Pedram. “An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read SNM modeling,” Springer Journal of Zhejiang University-SCIENCE C (Computers & Electronics), Vol. 13, No. 1, Jan. 2012, pp. 58-70.
  33. M. Ghasemazar and M. Pedram. “Optimizing the power-delay product of a linear pipeline by opportunistic time borrowing,” IEEE Trans. on Computer Aided Design, Vol. 30, No. 10, Oct. 2011, pp. 1493-1506.
  34. B. Ebrahimi, M. Rostami, A. Afzali-Kusha, and M. Pedram. “Statistical design optimization of FinFET SRAM using back-gate voltage,” IEEE Trans. on VLSI Systems,, Vol. 19, No. 10, Oct. 2011, pp. 1911-1916.
  35. M. E. Salehi, M. Samadi, M. Najibi, A. Afzali-Kusha, M. Pedram, and S. M. Fakhraie. “Dynamic voltage and frequency scheduling for embedded processors considering power/performance tradeoffs,” IEEE Trans. on VLSI Systems, Vol. 19, No. 10, Oct. 2011, pp. 1931-1935.
  36. S. Nazarian, H. Fatemi, and M. Pedram. “Accurate timing and noise analysis of combinational and sequential logic cells using current source modeling,” IEEE Trans. on VLSI Systems, Vol. 19, No. 1, Jan. 2011, pp. 92-103.
  37. H-R. Ahmadi, A. Afzali-Kusha, and M. Pedram. “A power-optimized secure low-energy elliptic-curve cryptography processor,” IEICE Electronics Express, Vol. 7, No. 23, 2010, pp.1752-1759.
  38. H-S. Jung and M. Pedram. “Supervised learning based power management for multicore processors,” IEEE Trans. on Computer Aided Design, Vol. 29, No. 9, Sept. 2010, pp. 1395-1408.
  39. P. Rong and M. Pedram. “A Markovian decision-based approach for extending the lifetime of a network of battery-powered mobile devices by remote processing,” Int’l Journal of Low Power Electronics, American Scientific Publishers, Vol. 6 No. 2, August 2010, pp. 227-239.
  40. E. Rokhsat, A. Afzali-Kusha, and M. Pedram. “A high-efficiency, auto mode-hop, variable-voltage, ripple control buck converter,”Journal of Power Electronics, Korean Institution of Power Electronics, Vol. 10, No. 2 Mar. 2010, pp. 115-124.
  41. G. Razavipour, A. Afzali-Kusha, and M. Pedram. “Design and analysis of two low-power SRAM cell structures,” IEEE Trans. on VLSI Systems, Vol. 17, No. 10, Oct. 2009, pp. 1551-1555.
  42. A. M. Rahmani, A. Afzali-Kusha, and M. Pedram. “Forecasting-based dynamic virtual channel management for power reduction in network-on-chips,” Journal of Low Power Electronics, Vol.5, No. 3, Oct. 2009, pp. 385-395
  43. A. M. Rahmani, A. Afzali-Kusha, and M. Pedram. “A novel synthetic traffic pattern for power/performance analysis of network-on-chips using negative exponential distribution,” Journal of Low Power Electronics, Vol.5, No. 3, Oct. 2009, pp. 396-405.
  44. H-S. Jung, A. Hwang, and M. Pedram. “Predictive-flow-queue based energy optimization for gigabit Ethernet controllers.” IEEE Trans. on VLSI Systems, Vol. 17, No. 8, Aug. 2009, pp. 1113-1126.
  45. H-S. Jung and M. Pedram. “Uncertainty-aware dynamic power management in partially observable domains,” IEEE Trans. on VLSI Systems, Vol. 17, No. 7, Jul. 2009, pp. 929-942.
  46. M. Saneei, A. Afzali-Kusha, Z. Navabi, and M. Pedram. “Two high performance and low power serial communication interfaces for on-chip interconnects,” Canadian Journal of Electrical and Computer Engineering, Vol. 34, No. 1/2, Winter/Spring 2009, pp. 49-56.
  47. B. Amelifard and M. Pedram. “Optimal design of the power delivery network for multiple voltage-island system-on-chips,” IEEE Trans. on Computer Aided Design, Vol. 28, No. 6, Jun. 2009, pp. 888-900.
  48. B. Amelifard, F. Fallah, and M. Pedram. “Low-power fanout optimization using multi threshold voltages and multi channel lengths,” IEEE Trans. on Computer Aided Design,, Vol. 28, No. 4, Apr. 2009, pp. 478-489.
  49. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram.“BZ-FAD: A low-power low-area multiplier based on shift-and-add architecture,” IEEE Trans. on VLSI Systems, Vol. 17, No.2, Feb. 2009, pp. 302-305.
  50. W-B. Lee, K. Patel, and M. Pedram. “White LED backlight control for motion blur reduction and power minimization in large LCD TV’s,” Journal of the Society for Information Display, Vol. 17, No. 1, Jan. 2009, pp. 37-45.
  51. E. Pakbaznia, F. Fallah, and M. Pedram. “Charge recycling in power-gated CMOS circuits,” IEEE Trans. on Computer Aided Design, Vol. 27, No. 10, Oct. 2008, pp. 1798-1811.
  52. S. Nazarian and M. Pedram. “Crosstalk-affected delay analysis in nanometer technologies,” Int’l Journal of Electronics, Taylor & Francis Publishers, Vol. 95, No. 9, Sep. 2008, pp. 903-937.
  53. B. Amelifard, F. Fallah and M. Pedram. “Leakage minimization of SRAM cells in a dual-Vt and dual-Tox technology,” IEEE Trans. on VLSI Systems, Vol. 16, No.7, Jul. 2008, pp. 851-860.
  54. W-B. Lee, K. Patel, and M. Pedram. “GOP-level dynamic thermal management in MPEG-2 decoding,” IEEE Trans. on VLSI Systems, Vol. 16, No.6, Jun. 2008, pp. 662-672.
  55. A. Abdollahi and M. Pedram. “Symmetry detection and Boolean matching utilizing a signature-based canonical form of Boolean functions,” IEEE Trans. on Computer Aided Design, Vol. 27, No.6, Jun. 2008, pp. 1128-1137.
  56. P. Rong and M. Pedram. “Energy-aware task scheduling and dynamic voltage scaling in a real-time system,” Int’l Journal of Low Power Electronics, American Scientific Publishers, Vol. 4, No. 1, Apr. 2008, pp. 1-10.
  57. A. Abbasian, S. Hatami, A. Afzali-Kusha, and M. Pedram. “Wavelet-based dynamic power management for nonstationary service requests,” ACM Trans. on Design Automation of Electronic Systems, Vol. 13, No. 1, Jan. 2008, pp. 13:1-13:41.
  58. H. Parandeh-Afshar, M. Saneei, A. Afzali-Kusha, and M. Pedram. “Fast INC-XOR codec for low power address buses,” IET Computers & Digital Techniques, Vol. 1, No. 5, Sep. 2007, 625-626.
  59. C-W. Kang, A. Iranli, and M. Pedram. “A synthesis approach for coarse-grained, antifuse-based FPGAs.” IEEE Trans. on Computer Aided Design, Vol. 26, No. 9, Sep. 2007, pp. 1564-1575.
  60. S. Abbaspour, H. Fatemi, and M. Pedram. “Parameterized block-based non-Gaussian variational gate timing analysis,” IEEE Trans. on Computer Aided Design, Vol. 26, No. 8, Aug. 2007, pp. 1495-1508.
  61. A. Abdollahi, F. Fallah, and M. Pedram. “A robust power gating structure and power mode transition strategy for MTCMOS design,” IEEE Trans. on VLSI Systems, Vol. 15, No., 1, Jan. 2007, pp. 80-89.
  62. D. Hammerstrom, J. Harlow, I. Bahar, W. H. Joyner, C. Lau, D. Marculescu, A. Orailoglu, M. Pedram. “Architectures for Silicon nanoelectronics and beyond,” IEEE Computer Magazine, Jan. 2007, pp. 62-70.
  63. S. Abbaspour, M. Pedram, and A.H. Ajami, “Fast interconnect and gate timing analysis for performance optimization.” IEEE Trans. on VLSI Systems, Vol. 14, No. 12, Dec. 2006, pp. 1383-1388.
  64. A. Iranli and M. Pedram. “Cycle-based decomposition of Markov chains with applications to low power synthesis and sequence compaction for finite state machines.”  IEEE Trans. on Computer Aided Design, Vol. 25, No. 12, Dec. 2006, pp. 2712-2725.
  65. A. Iranli, W-B. Lee, and M. Pedram. “HVS-Aware Dynamic Backlight Scaling in TFT LCD’s.”  IEEE Trans. on VLSI systems, Vol. 14, No. 10, Oct. 2006, pp. 1103-1116.
  66. M. Pedram and S. Nazarian, “Thermal modeling, analysis and management in VLSI circuits: principles and methods.”  Proc. of IEEE, Special Issue on Thermal Analysis of ULSI, Vol. 94, No. 8, Aug. 2006, pp. 1487-1501.
  67. P. Rong and M. Pedram. “Battery-aware power management based on Markovian decision processes.”  IEEE Trans. on Computer Aided Design, Vol. 25, No. 7, Jul. 2006, pp. 1337-1349.
  68. P. Rong and M. Pedram. “An analytical model for predicting the remaining battery capacity of Lithium-ion batteries.”  IEEE Trans. on VLSI systems, Vol. 14, No. 5, May 2006, pp. 441-451.
  69. P. Heydari and M. Pedram. “Model-order reduction using variational balanced truncation with spectral shaping.”  IEEE Trans. on Circuits and Systems I, Vol. 53, No. 4, Apr. 2006, pp. 879-891. (Best Paper Award)
  70. C-W. Kang and M. Pedram. “A leakage-aware low power technology mapping algorithm considering the hot-carrier effect.”  Int’l Journal of Low Power Electronics, American Scientific Publishers, Vol. 1, No. 2, pp. 133-144, Aug. 2005.
  71. M. Pedram and A. Abdollahi, “Low power RT-level synthesis techniques: a tutorial.”  IEE Proc. on Computers and Digital Techniques, Vol. 152, No. 3, pp. 333-343, May 2005.
  72. A. H. Ajami, K. Banerjee, and M. Pedram. “Modeling and analysis of non-uniform substrate temperature effects in high performance VLSI.”  IEEE Trans. on Computer Aided Design, Vol. 24, No. 6, Jun. 2005, pp. 849-861.
  73. F. Fallah and M. Pedram. “Standby and active leakage current control and minimization in CMOS VLSI circuits.”  IEICE Trans. on Electronics, Special Section on Low-Power LSI and Low-Power IP, Vol. E88-C, No. 4 Apr. 2005, pp. 509-519.
  74. K. Choi, W-C. Cheng, and M. Pedram “Frame-based dynamic voltage and frequency scaling for an MPEG player.”  Journal of Low Power Electronics, American Scientific Publishers, Vol. 1, No. 1, Apr. 2005, pp. 27-43.
  75. K. Choi, K. Kim, and M. Pedram “Energy-aware MPEG-4 FGS streaming.”  Journal of Low Power Electronics, American Scientific Publishers, Vol. 1, No. 1, Apr. 2005, pp. 44-51.
  76. A. Ajami, K. Banerjee, and M. Pedram. “Scaling analysis of on-chip power grid voltage variations in nanometer scale ULSI.”  Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, Mar. 2005, pp. 277-290.
  77. P. Heydari and M. Pedram. “Capacitive crosstalk noise in high speed VLSI circuits.”  IEEE Trans. on Computer Aided Design, Vol. 24, No. 3, Mar. 2005, pp.478-488.
  78. K. Choi, R. Soma, and M. Pedram. “Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times.”  IEEE Trans. on Computer Aided Design, Vol. 24, No. 1, Jan. 2005, pp.18-28.
  79. H. Shim, N. Chang, and M. Pedram. “A backlight power management framework for the battery-operated multi-media systems.”  IEEE Design and Test Magazine, Sep./Oct. 2004, pp. 388-396.
  80. P. Heydari, S. Abbaspour and M. Pedram. “Interconnect energy dissipation in high-speed ULSI circuits.”  IEEE Trans. on Circuits and Systems I, Vol. 51, No. 8, Aug. 2004, pp. 1501-1514.
  81. Y. Aghaghiri, F. Fallah, and M. Pedram. “Transition reduction in memory buses using sector-based encoding techniques.”  IEEE Trans. on Computer Aided Design, Vol. 23, No. 8, Aug. 2004, pp. 1164-1174.
  82. W-C. Cheng and M. Pedram. “Chromatic encoding: a low power encoding technique for Digital Visual Interface.”  IEEE Trans. on Consumer Electronics, Vol. 50, No. 1, Feb. 2004, pp. 320-328.
  83. W-C. Cheng and M. Pedram. “Power minimization in a backlit TFT-LCD display by concurrent brightness and contrast scaling.”  IEEE Trans. on Consumer Electronics, Vol. 50, No. 1, Feb. 2004, pp. 25-32.
  84. A. Abdollahi, F. Fallah, and M. Pedram. “Leakage current reduction in CMOS VLSI circuits by input vector control.”  IEEE Trans. on VLSI Systems, Vol. 12, No. 2, Feb. 2004, pp.140-154.
  85. P. Rezvani and M. Pedram. “A fanout optimization algorithm based on the effort delay model.”  IEEE Trans. on Computer Aided Design, Vol. 22, No. 12, Dec. 2003, pp. 1671-1677.
  86. P. Heydari and M. Pedram. “Ground bounce in digital VLSI circuits,”  IEEE Trans. on VLSI Systems, Vol. 11, No. 2, Apr. 2003, pp. 180-193.
  87. M. Pedram and Q. Wu. “Design considerations for battery-powered electronics,”  IEEE Trans. on VLSI Systems, Vol. 10, No. 5, Oct. 2002, pp. 601-607.
  88. Y. Aghaghiri, F. Fallah and M. Pedram. “A class of irredundant encoding techniques for reducing bus power,”  Special Issue on Low Power Design in Journal of Circuits, Systems, and Computers, World Scientific Publishers, Vol. 11, No. 5 (2002) pp. 445-457.
  89. W-C. Cheng and M. Pedram. “Power-aware bus encoding techniques for I/O and data busses in an embedded system,”  Special Issue on Power IC Design in Journal of Circuits, Systems, and Computers, World Scientific Publishers, Vol. 11, No. 4 (2002), pp. 351-363.
  90. X. Wu, G. Hang and M. Pedram. “Low power DCVSL circuits employing AC power supply,”  Science in China, Vol. 45, No. 3 (2002), pp. 232-242.
  91. W-C. Cheng and M. Pedram. “Power-optimal encoding for a DRAM address bus,”  IEEE Trans. on VLSI Systems, Vol. 10, No. 2, Apr. 2002, pp. 109-118.
  92. A. Salek, J. Lou and M. Pedram. “Hierarchical buffered routing tree generation,”  IEEE Trans. on Computer Aided Design, Vol. 21, No. 5, May 2002, pp. 554-567.
  93. C-T. Hsieh and M. Pedram. “Architectural power optimization by bus splitting,”  IEEE Trans. on Computer Aided Design, Vol. 21, No. 4, Apr. 2002, pp. 408-414.
  94. X. Wu, B. Chen and M. Pedram. “Power estimation in CMOS circuits based on multiple-valued logic,”  Journal of Multiple Valued Logic, Gordon and Breach Publishing Group, Vol.7, No. 3-4 (2001), pp. 195-211.
  95. Q. Qiu, Q. Wu and M. Pedram. “Stochastic modeling of a power-managed system: construction and optimization,”  IEEE Trans. on Computer Aided Design, Vol. 20, No. 10, Oct. 2001, pp. 1200-1217.
  96. Q. Wu, Q. Qiu and M. Pedram. “Estimation of peak power dissipation in VLSI circuits using the limiting distributions of extreme order statistics,”  IEEE Trans. on Computer Aided Design, Vol. 20, No. 8, Aug. 2001, pp. 942-956.
  97. X. Wu and M. Pedram. “Low-power sequential circuit design using T flip-flops,”  Int’l Journal of Electronics, Taylor and Francis Publishing Group, Vol. 88, No.6, Jun. 2001, pp. 635-643.
  98. J. Oh and M. Pedram. “Gated clock routing for low power microprocessor design,”  IEEE Trans. on Computer Aided Design, Vol. 20, No. 6, Jun. 2001, pp. 715-722.
  99. H. Vaishnav and M. pedram. “Alphabetic trees: theory and applications in layout-driven logic synthesis,”  IEEE Trans. on Computer Aided Design, Vol. 20, No. 1, Jan. 2001, pp. 58-69.
  100. C-S. Ding, C-T. Hsieh and M. Pedram. “Improving efficiency of the Monte Carlo power estimation,”  IEEE Trans. on VLSI Systems, Vol. 8, No. 5, Oct. 2000, pp. 584-593.
  101. X. Wu, M. Pedram, and L. Wang,“Multi-code state assignment for low power design,”  IEE Proc.-Circuits, Devices and Systems, Vol. 147, No. 5, Oct. 2000, pp. 271-275.
  102. J. Chang and M. Pedram. “Codex-DP: Codesign of communicating systems using dynamic programming,”  IEEE Trans. on Computer Aided Design, Vol. 19, No. 7, Jul. 2000, pp. 732-744.
  103. R. Marculescu, D. Marculescu and M. Pedram. “Stochastic sequential machine synthesis with application to constrained sequence generation,”  ACM Trans. on Design Automation of Electronic Systems, Vol. 5, No. 3, Jul. 2000, pp. 658-681.
  104. D. Marculescu, R. Marculescu and M. Pedram. “Theoretical bounds for switching activity analysis in finite-state machines,”  IEEE Trans. on VLSI Systems, Vol. 8, No. 3, Jun. 2000, pp. 335-339.
  105. Q. Wu, M. Pedram and X. Wu. “Clock-gating and its application to low power design of sequential circuits,”  IEEE Trans. on Circuits and Systems, Part 1, Vol. 47, No. 3, Mar. 2000, pp. 415-420.
  106. P. Cocchini and M. Pedram. “Fanout optimization using bipolar LT-trees,”  IEEE Trans. on Computer Aided Design, Vol. 19, No. 3, Mar. 2000, pp. 339-349.
  107. W. Chen, C-T. Hsieh and M. Pedram. “Simultaneous gate sizing and placement,”  IEEE Trans. on Computer Aided Design, Vol. 19, No. 2, Feb. 2000, pp. 206-214.
  108. X. Wu and M. Pedram. “Bounded algebra and current-mode digital circuits,”  Journal of Computer Science and Technology, Vol. 14, No. 6, Nov. 1999, pp. 551-557.
  109. M. Pedram and B. T. Preas, “Interconnection analysis for standard cell layouts,”  IEEE Trans. on Computer Aided Design, Vol. 18, No. 10, Oct. 1999, pp. 1512-1518.
  110. X. Wu, Q. Qiu and M. Pedram. “A synthesis methodology for ECL circuits based on mixed voltage-current representation,”  Journal of Electronics, Vol. 16, No. 4, Oct. 1999, pp. 359-366.
  111. A. Salek, J. Lou and M. Pedram. “An integrated logical and physical design flow for deep submicron circuits,”  IEEE Trans. on Computer Aided Design, Vol. 18, No. 9, Sep. 1999, pp. 1305-1315.
  112. R. Marculescu, D. Marculescu and M. Pedram. “Sequence compaction for power estimation: Theory and practice,”  IEEE Trans. on Computer Aided Design, Vol. 18. No. 7, Jul. 1999, pp. 973-993.
  113. H. Vaishnav and M. Pedram. “Delay optimal partitioning targeting low power VLSI circuits,”  IEEE Trans. on Computer Aided Design, Vol. 18. No. 6, Jun. 1999, pp. 799-812.
  114. X. Wu, Q. Wu and M. Pedram. “Synchronous derived clock and synthesis of low power sequential circuits,”  Journal of Electronics, Vol. 16, No. 2, Apr. 1999, pp. 130-145.
  115. C-Y. Tsui, M. Pedram.and A. M. Despain.“Low power state assignment targeting two and multilevel logic implementations,”  IEEE Trans. on Computer Aided Design, Vol. 17. No. 12, Dec. 1998, pp. 1281-1291.
  116. Q. Wu, Q. Qiu, M. Pedram and C-S. Ding. “Cycle-accurate macro-models for RT-level power analysis,”  IEEE Trans. VLSI Systems,, Vol. 6, No. 4, Dec. 1998, pp. 520-528.
  117. C-S. Ding, C-Y. Tsui and M. Pedram. “Gate-level power estimation using tagged probabilistic simulation,”  IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, Nov. 1998, pp. 1099-1107.
  118. C-T. Hsieh and M. Pedram. “Micro-processor power estimation using profile-driven program synthesis,”  IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, Nov. 1998, pp. 1080-1089.
  119. E. Macii, M. Pedram and F. Somenzi. “High level power modeling, estimation and optimization,”  IEEE Trans. on Computer Aided Design, Vol. 17. No. 11, Nov. 1998, pp. 1061-1079.
  120. C-Y. Tsui and M. Pedram. “Accurate and efficient power simulation strategy by compacting the input vector set,”  Integration, the VLSI Journal, Vol. 25 (1998), pp. 37-52.
  121. C-S. Ding, Q. Wu, C-T. Hsieh and M. Pedram. “Stratified random sampling for power evaluation,”  IEEE Trans. on Computer Aided Design, Vol. 17, No. 6, Jun. 1998, pp. 465-471.
  122. R. Marculescu, D. Marculescu and M. Pedram. “Probabilistic modeling of dependencies during switching activity analysis,”  IEEE Trans. on Computer Aided Design, Vol. 17, No. 2, Feb. 1998, pp. 73-83.
  123. S. Liu, M. Pedram and A. M. Despain. “State assignment based on two-dimensional placement and hypercube mapping,”  Integration, the VLSI Journal, Vol. 24 (1997), pp. 101-118.
  124. J.-M. Chang and M. Pedram. “Energy Minimization Using Multiple Supply Voltages,”  IEEE Trans. on VLSI Systems, Vol. 5. No. 4, Dec. 1997, pp. 436-443.
  125. R. Marculescu, D. Marculescu and M. Pedram. “Vector compaction using dynamic Markov models,”  IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No. 10, Oct. 1997.
  126. M. Pedram and X. Wu, “A new description of CMOS circuits at switch-level with applications,”  IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No. 10, Oct. 1997.
  127. J. Oh, I. Pyo and M. Pedram. “Constructing minimal spanning/Steiner trees with bounded path length,”  Integration, the VLSI Journal, Vol. 22 (1997), pp. 137-163.
  128. M. Pedram. N. Bhat and E. S. Kuh, “Combining technology mapping and layout,”  The VLSI Design: An Int’l Journal of Custom-Chip Design, Simulation and Testing, Vol. 5, No. 2 (1997), pp. 111-124.
  129. P. Tafertshofer and M. Pedram. “Factored edge-valued binary-decision diagrams,”  Formal Methods in System Design, Kluwer Academic Publishers, Vol. 10, No. 2/3 (1997), pp. 137-164.
  130. M. Pedram and H. Vaishnav, “Power optimization in VLSI layout: A survey,”  The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Kluwer Academic Publishers, Vol. 15, No. 3 (1997), pp. 221-232.
  131. S. Iman and M. Pedram. “An approach for multi-level logic optimization targeting low power,”  IEEE Trans. on Computer Aided Design, Vol. 15, No. 8 (1996), pp. 889-901.
  132. Y-T. Lai, K-R. Pan and M. Pedram. “OBDD-based function decomposition: Algorithms and implementation,”  IEEE Trans. on Computer Aided Design, Vol. 15, No. 8 (1996), pp. 977-990.
  133. D. Marculescu, R. Marculescu and M. Pedram. “Information theoretic measures for power analysis,”  IEEE Trans. on Computer Aided Design, Vol. 15, No. 6 (1996), pp. 599-610.
  134. Y-T. Lai, M. Pedram and S. B. K. Vrudhula, “Formal verification using edge-valued binary decision diagrams,”  IEEE Trans. on Computers, Vol. 45, No. 2 (1996), pp. 247-255.
  135. M. Pedram. “Power minimization in IC design: Principles and applications,”  ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 1 (1996), pp. 3-56.
  136. K. Chaudhary and M. Pedram. “Computing the area versus delay trade-off curves in technology mapping,”  IEEE Trans. on Computer Aided Design, Vol. 14, No. 12 (1995), pp. 1480-1489.
  137. C-Y. Tsui, J. Monteiro, M. Pedram. S. Devadas, A. M. Despain and B. Lin, “Power estimation in sequential logic circuits,”  IEEE Trans. on VLSI Systems, Vol. 3, No. 3 (1995), pp. 404-416 (1996 IEEE Circuits and Systems Society VLSI Systems Trans. (Best Paper Award)
  138. D. Singh, J. Rabaey, M. Pedram. F. Catthoor, S. Rajgopal, N. Sehgal and T. Mozdzen, “Power-conscious CAD tools and methodologies: A perspective,”  Proc. of the IEEE, Vol. 83, No. 4 (1995), pp. 570-594.
  139. M. Pedram. B. S. Nobandegani and B. T. Preas, “Design and analysis of segmented routing channels for row-based FPGAs,”  IEEE Trans. on Computer Aided Design, Vol. 13, No. 12 1994, pp. 1470-1479.
  140. M. Pedram. “Low power CAD: Trends and challenges,”  White paper on low power LSI technology, Nikkei Microdevices, Nikkei Business Publications, Inc., Oct. 1994, pp. 129-139.
  141. M. Pedram. “Power estimation and optimization at the logic level,”  Int’l Journal of High Speed Electronics and Systems, Vol. 5, No. 2 (1994), pp. 179-202.
  142. Y-T. Lai, M. Pedram and S. B. K. Vrudhula, “EVBDD-based algorithms for integer linear programming, spectral transformation and function decomposition,”  IEEE Trans. on Computer Aided Design, Vol. 13, No. 8 (1994), pp. 959-975.
  143. C-Y. Tsui, M. Pedram and A. M. Despain, “Power efficient technology decomposition and mapping under an extended power consumption model,”  IEEE Trans. on Computer Aided Design, Vol. 13, No. 9 (1994), pp.1110-1122.
  144. M. Pedram and E. S. Kuh, “BEAR-FP: A robust framework for floorplanning,”  Int’l Journal of High Speed Electronics and Systems, Vol. 3, No. 1 (1992), pp. 137-170.
  145. W-W. Dai, B. Eschermann, E.S. Kuh and M. Pedram. “Hierarchical placement and floorplanning for BEAR,”  IEEE Trans. on Computer Aided Design, Vol. 8, No. 12 (1989), pp. 1335-1349.
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