Mehdi Saeedi

University of Southern California
Department of EE-Systems, EEB-200
3740 McClintock Ave.
Los Angeles CA 90089

Email:
msaeedi AT usc.edu

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Papers refered by DBLP, delayed by several months
Papers refered by Google Scholar
Papers on arXiv

Preprint

  1. Mehdi Saeedi and Igor L. Markov, "Quantum Circuits for GCD Computation with $O(n \log n)$ Depth and O(n) Ancillae", 2013 (arXiv:1304.7516).

Journal Papers

  1. Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram, "Cofactor Sharing for Reversible Logic Synthesis.", ACM Journal of Emerging Technologies in Computing Systems, In Press, 2014. ()

  2. Mehdi Saeedi and Massoud Pedram, "Linear-Depth Quantum Circuits for n-qubit Toffoli gates with no Ancilla", Physical Review A , 87, 062318, 2013 (arXiv:1303.3557).

  3. Afshin Abdollahi, Mehdi Saeedi, and Massoud Pedram, "Reversible Logic Synthesis by Quantum Rotation Gates," Quantum Information and Computation , Vol. 13, No. 9-10, pp. 0771-0792, 2013 (arXiv:1302.5382).

  4. Igor L. Markov and Mehdi Saeedi, "Faster Quantum Number Factoring via Circuit Synthesis," Physical Review A , 87, 012310, 2013 (arXiv:1301.3210).

  5. Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, "Depth-Optimized Reversible Circuit Synthesis," Quantum Information Processing, Vol. 12, No. 4, pp. 1677-1699, 2013 (arXiv:1208.5425).

  6. Mehdi Saeedi, Igor L. Markov, "Synthesis and Optimization of Reversible Circuits - A Survey", ACM Computing Surveys, 45, 2, Article 21 (34 pages), 2013. (arXiv:1110.2574)

  7. Igor L. Markov and Mehdi Saeedi, "Constant-optimized Quantum Circuits for Modular Multiplication and Exponentiation," Quantum Information and Computation, Vol. 12, No. 5&6, pp. 0361-0394, 2012 (arXiv:1202.6614).

  8. Dmitri Maslov, Mehdi Saeedi, "Reversible Circuit Optimization via Leaving the Boolean Domain", IEEE Trans. on Computer-Aided Design, Vol. 30, No. 6, pp. 806 - 816, 2011 (arXiv:1103.0215).

  9.  Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, "Block-Based Quantum-Logic Synthesis," Quantum Information and Computation, Vol.11 No.3&4, pp. 0262-0277, 2011 (arXiv:1011.2159).

  10. Mehdi Saeedi, Robert Wille, Rolf Drechsler, “Synthesis of Quantum Circuits for Nearest Neighbor Architectures,” Quantum Information Processing, Springer, Vol. 10, No. 3, pp. 355-377, 2011 (arXiv:1110.6412) The final publication is available here.

  11. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian “Reversible Circuit Synthesis Using a Cycle-Based Approach,” ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, Issue 4, Article 13, December 2010. (arXiv:1004.4320).

  12. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, "A Library-Based Synthesis Methodology for Reversible Logic," Microelectronics Journal, Elsevier, Volume 41, No. 4, pp. 185–194, 2010 (arXiv:1004.1697).

  13. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “CNOT-Based Quantum Circuit Synthesis Based on Matrix Characterization,” IEICE Transactions on Electronics Express, Vol. 5, No. 17, pp. 638-643, 2008 (link).

  14. Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani, "Towards a Thorough Set of Metrics for Quantum Circuit Synthesis," International Journal of Physics, Serial Publications, Vol. 1, No. 1-2, January-December, pp. 9-22, 2008.

  15.  Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani, “A Fast IP Routing Lookup Architecture for Multi-Gigabit Switching Routers Based on Reconfigurable Systems,” Microprocessors and Microsystems Journal, Elsevier, Volume 32, Issue 4, pp. 223-233, 2008 (link).

  16.  Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, “Evaluation, Prediction and reduction of routing congestion,” Microelectronics Journal, Volume 38, Issue 8-9, pp. 942-958, August 2007 (link).

International Conference Papers

  1. Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram, "Optimization of Qubit-to-Qubit Interactions in 2D Quantum Architectures ", Asia and South Pacific Design Automation Conference (ASPDAC), 2014. ()

  2. Mehdi Saeedi, Alireza Shafaei, and Massoud Pedram, "Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures ", Conference on Reversible Computation (RC), 2013 (arXiv:1304.0432).

  3. Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram, "Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures ", Design Automation Conference (DAC), 2013. ()

  4. Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram, "Reversible Logic Synthesis of k-Input, m-Output Lookup Tables", Design Automation and Test in Europe (DATE), 2013.( ) ()

  5. Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, "Logical-Depth-Oriented Reversible Logic Synthesis", International Workshop on Logic & Synthesis (IWLS), 2011.() ()

  6. Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani, “Rule-Based Optimization of Reversible Circuits,” Asia and South Pacific Design Automation Conference (ASPDAC), pp. 849 – 854, 2010 (arXiv:1004.1755) () .

  7. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “A Library-Based Synthesis Approach for Reversible Logic,” International Workshop on Logic & Synthesis (IWLS), USA, 2009 ().

  8. Robert Wille, Mehdi Saeedi, Rolf. Drechsler, “Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost,” International Workshop on Logic & Synthesis (IWLS), USA, 2009 (arXiv:1004.4609).

  9. Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “A Cycle Based Synthesis Algorithm for Reversible Logic,” Asia and South Pacific Design Automation Conference (ASPDAC), 2009 (link) (see the extended version arXiv:1004.4320) () .

  10. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “Moving Forward: A Non-Search Based Synthesis Method toward Efficient CNOT-Based Quantum Circuit Synthesis Algorithms,” Asia and South Pacific Design Automation Conference (ASPDAC), pp. 83-88, 2008 (link) ().

  11. Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani, "Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics," EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD), 2008 (link).

  12. Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi, “Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement,” International Symposium on VLSI (ISVLSI), pp. 467-470, 2008 (link).

  13. Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “FPGA-Based Circuit Model Emulation of Quantum Algorithms,” International Symposium on VLSI (ISVLSI), pp. 399-404, 2008 (link) ().

  14. Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani, “Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions,” International Symposium on VLSI (ISVLSI), pp. 471-474, 2008 (link).

  15. Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi, "Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm," EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD), 2008 (link).

  16. Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi "An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty," EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD), 2008 (link).

  17. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “A Novel Synthesis Algorithm for Reversible Circuits,” International Conference on Computer-Aided Design (ICCAD), pp. 65-68, USA, 2007 (arXiv:0801.0802) ().

  18. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “On the Behavior of Substitution-Based Reversible Circuit Synthesis Algorithms: Investigation and Improvement,” International Symposium on VLSI (ISVLSI), pp. 428-436, Brazil, 2007 (link) ().

  19. HamidReza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi, “An Efficient Analytical Approach to Path-Based Buffer Insertion,” International Symposium on VLSI (ISVLSI), pp. 219-224, Brazil, 2007 (link).

  20. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “A New Methodology for Quantum Circuit Synthesis: CNOT-Based Circuits as an Example,” International Workshop on Logic & Synthesis (IWLS), pp. 396-403, USA, 2007.

  21. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis,” EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD), pp. 339-346, Germany, 2007 (arXiv:0712.2963).

  22. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “A Forward-Looking Non-Search Based Synthesis Algorithm for Reversible Circuits,” IEEE East-West Design & Test Symposium, Armenia (EWDTS), 2007, (Best Regular Paper).()

  23. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, “Prediction and reduction of routing congestion,” International Symposium on Physical Design (ISPD), pp. 72-77, USA, 2006 ().

  24. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, “An efficient congestion reduction algorithm based on contour plotting,” International Conference on Microelectronic (ICM), Pakistan, 2005 (link).

  25. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, “Congestion prediction: from metrics definition to routing estimation,” International Conference on Microelectronic (ICM), pp. 183- 188, Pakistan, 2005 (link).

  26. Mehdi Saeedi, Morteza Saheb Zamani, “A true congestion prediction method based on router's intelligence,” International Symposium on Communications and Information Technology (ISCIT), Volume 2, Issue 12-14, pp. 1199-1202, China, 2005 (link).

National Conference Papers (in Persian)

  1. Ali Arabi, Morteza Saheb Zamani, Mehdi Saeedi "Congestion Alleviation on logic synthesis," Iranian Conference on Electrical Engineering, Iran, 2008. ()

  2. Ali Arabi, Morteza Saheb Zamani, Mehdi Saeedi, “Technology Mapping Using Partitioning Information for Congestion Reduction,” Computer Society of Iran Computer Conference, Kish Island, Iran, 2008.()

  3. Aida Vosoughi, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, “Hardware Implementation of TC-Encapsulation in the EFM Standard,” Computer Society of Iran Computer Conference, Kish Island, Iran, 2008.()

  4. Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, “Emulation of Quantum Circuits with FPGA,” Computer Society of Iran Computer Conference, Kish Island, Iran, 2008.()

  5. Mojtaba Karami, Mehdi Saeedi, Morteza Saheb Zamani, Mohammad Rahmati, “Improved the WMBPM Motion Estimation Algorithm with its Efficient Hardware Architecture,” Computer Society of Iran Computer Conference, pp. 1812- 1815, Iran, 2007.()

  6. Mohammad H. Montazeri, Mohsen Taheri, Mehdi Saeedi, Hassan Taheri, Morteza Saheb Zamani, “An Efficient Hardware Architecture for Model Predictive Controllers,” Computer Society of Iran Computer Conference, pp. 1105-1111, Iran, 2007.()

  7. Mehdi Saeedi, Morteza Saheb Zamani, Saadat Pourmozafari, “The Effects of Process Variation on Noise Avoidance Techniques in VLSI Circuits,” Computer Society of Iran Computer Conference, pp. 896-903, Iran, 2007.()

  8. Behnam Ghavami, Arash Mehdizadeh, Mehdi Saeedi, Morteza Saheb Zamani, “An Efficient Heterogeneous Architecture for the Reconfigurable unctional Unit of Extensible Processors,” Computer Society of Iran Computer Conference, pp. 1112-1119, Iran, 2007.()

  9. Mehdi Saeedi, Mehdi Dehghan, “A Time-Variant Log-Based Fault Tolerance Technique in Embedded Systems,” Computer Society of Iran Computer Conference, pp. 811-818, Iran, 2007.()

  10. Mahmoud Aghapour, Mehdi Saeedi, Morteza Saheb Zamani, “Global Routing with crosstalk consideration,” Computer Society of Iran Computer Conference, Iran, 2006.()

  11. Parisa Khadem Hamedani, Mehdi Saeedi, Morteza Saheb Zamani, “Incremental placement algorithm for performance improvement,” Computer Society of Iran Computer Conference, Iran, 2006.()

  12. Mehdi Saeedi, Morteza Saheb Zamani, “Crosstalk reduction during placement based on contour plotting,” Computer Society of Iran Computer Conference, Iran, 2006.()

PhD Thesis (in Persian)

Mehdi Saeedi, “Proposing a quantum circuit synthesis methodology based on a building block library,” Tehran Polytechnic, Iran, 2010.()

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