Individual Project #2
Logic Simulation (referred to as phase #1)
You can find inputs/outputs used for grading in
this link. For each circuit, 10 test patterns are used.
Common mistakes:
- c499 is failing: XOR gate was not implemented correctly.
- c880, c1355, c1908, c3540, and c5315 are failing: BUFF gate was not implemented.
- Implementation of the levelization algorithm can be wrong.
- Many of the implementations are not deallocating the dynamically
allocated memory. This will cause serious issues!
- A time limit (higher than 1s) strongly suggests that your algorithm is not correct.
Results
Deadline #1
We will not consider the circuits with "Buffer" gates for this deadline, i.e. c880, c1355, c1908, c3540, and c5315.
Deadline #2
All circuits will be considered. Time limit is set to 1 second.