Short Biography:

I received my B.Sc. in Electrical Engineering and M.Sc. in Electronics (Circuit and System) from University of Tehran, Iran, in 2005 and 2008 respectively. I am currently working toward the PhD degree in Electrical Engineering at University of Southern California under supervision of Prof. Masoud Pedram. My research is in the area of VLSI design and CAD. I am specifically working on statistical timing analysis and optimization in VLSI circuits and systems.

Research Interests:

• Statistical timing analysis and optimization in VLSI circuits

•  Low power digital integrated circuit design

• Computational digital circuits and memory design

Publications:

Journal papers

1. F. Kashfi, S. Mehdi Fakhraie, and S.Safari "Designing an ultra-high-speed multiply-accumulate structure," Microelectronics Journal, Vol. 39, No. 12, pp. 1476-1484, Dec 2008.
2. F. Kashfi, A. Agah, S. Mehdi Fakhraie, and S.Safari "15GHz Carrylook-Ahead Low-Voltage-Swing Adder," IEICE Electronics Express, vol. 4, no. 22, pp 696-700, (2007).

Conference papers

1. F. Kashfi, S. Mehdi Fakhraie, and S.Safari "A 65nm 10GHz pipelined MAC Structure," accepted in IEEE ISCAS'08, pp-460-463, May 2008.
2. F. Kashfi, and N. Masoumi, "Optimization of speed and power in a 16-bit carry skip adder in 70nm technology," IEEE MESCAS'06, Porto Rico, Aug. 2006.
3. F. Kashfi, and S. Mehdi Fakhraie, "Implementation of a high-speed low-power 32-bit adder in 70nm technology," IEEE ISCAS'06, Greece, May 2006 .

Honors:

•  Viterbi School Dean's Doctoral Fellowships Award,University of Southern California  2008-2009.