Operating Voltage: Super-threshold Near-threshold

SRAM Cell Type: Standard 6T Standard 8T

Interconnect Source: Ron Ho's PhD thesis (2003) ITRS data (2012)


Memory type: Cache (with tag array) Scratch RAM (similar to register file)

Cache Size (bytes, power of 2 integer):

Line Size (bytes, power of 2 integer >= 64):


Nr. of Banks:  

  You can find the source code of PCACTI here.
  This work and the corresponding releases was sponsored in part by a research contract from DARPA MTO (PERFECT program).
Report (download detailed report)
Access time:
Cycle time:
Total dynamic read energy per access:
Total dynamic write energy per access:
Total leakage power of a bank:
Cache height x width:
Cache area: